The latest update to the Universal Chiplet Interconnect Express (UCIe) specification — version 3.0 — introduces support for digital signal processor (DSP) interoperability and significantly boosts bandwidth, targeting emerging needs in AI, HPC, and wireless infrastructure.
In an interview with EE Times, Debendra Das Sharma, chairman of the UCIe Consortium, said that version 3.0 reflects the demands of its 140 member companies and the growing diversity of chiplet ecosystems. “We basically double the data rate with the planar interconnect, and that’s because people can’t get enough bandwidth,” Das Sharma explained. “If the bump is reduced, then my bandwidth actually quadruples.”
Expanding the Chiplet Ecosystem #
UCIe 3.0 doubles the data rates to 48 GT/s for UCIe-S and 64 GT/s for UCIe-A, achieving roughly 2× bandwidth density while maintaining similar power efficiency. The update builds upon previous releases — UCIe 1.1’s automotive compliance and UCIe 2.0’s support for 3D chiplets and enhanced testability — by addressing new workloads in AI and analog-digital integration.
The consortium’s focus remains on low power and high density, critical for AI-intensive data centers and edge computing applications. Power savings are realized through runtime recalibration and L2 optimization, which allow efficient link tuning and reduced idle power consumption.
DSP Support: A New Market Segment #
A key addition in UCIe 3.0 is support for DSP-based systems, enabling direct interconnect between SoCs and DSP chiplets. Das Sharma noted that “there was an overwhelming request for this kind of support,” particularly from DSP vendors dealing with analog sensitivity and power conversion challenges.
The update allows high-speed data transmission protocols between data converters to be mapped to UCIe Raw mode, removing the need for separate PLLs and minimizing frequency noise in sensitive circuits. Enhancements to the RDI/FDI interfaces and reuse of Retimer encodings for synchronization further streamline integration.
These improvements open up UCIe adoption for wireless infrastructure, software-defined radio (SDR), and radar systems — industries where DSPs play a central role.
Manageability and Efficiency Upgrades #
To complement the bandwidth increase, UCIe 3.0 also introduces several manageability enhancements, including:
- Early firmware download
- Sideband priority packets and extended reach
- Open-drain pin support
- Fast throttle and coordinated shutdown
These capabilities ensure that chiplets across a system can synchronize power and performance states dynamically, improving overall system resilience and efficiency.
Toward a Fully Open Chiplet Ecosystem #
Looking ahead, the UCIe Consortium is emphasizing open chiplet ecosystems and ubiquitous interconnects across multiple domains — from server AI and HPC to automotive and consumer electronics. Das Sharma summarized this direction succinctly: “We are establishing a universal language for chiplets, so innovation can scale freely across architectures and vendors.”
With its broadened scope and deeper system integration support, UCIe 3.0 marks a pivotal step toward unifying chiplet-based design, bringing DSPs, SoCs, and accelerators under one scalable and power-efficient interconnect framework.