With the rapid growth of cloud computing, high-performance computing (HPC), and artificial intelligence, demand for advanced computational capabilities continues to climb. At the same time, the complexity and cost of semiconductor design and manufacturing are increasing, driving the widespread adoption of chiplet architectures.
Over the years, SoC vendors such as Intel and AMD have advanced chiplet technologies to integrate smaller, reusable chips into modular architectures, boosting efficiency, flexibility, and customization. However, many chiplet-based solutions have relied on proprietary interconnect technologies, limiting broader adoption.
To address this challenge, the Universal Chiplet Interconnect Express (UCIe) consortium was founded in 2022. Its founding members include industry leaders such as Intel, AMD, Qualcomm, and TSMC, alongside hyperscalers like Google Cloud, Meta, and Microsoft. The goal is to establish a unified chiplet interconnect standard, enabling chips from different vendors, fabs, and functionalities to be seamlessly integrated within the same package. That same year, the UCIe 1.0 specification was introduced.
UCIe 3.0: Performance and Energy Efficiency Upgrades #
Now with more than 140 member companies, the consortium has officially released the UCIe 3.0 specification, delivering major improvements in performance, energy efficiency, and management features, while ensuring backward compatibility.
The most significant update is the bandwidth boost:
- Data rates up to 48 GT/s and 64 GT/s, doubling the bandwidth of UCIe 2.0 (32 GT/s), which launched in 2024.
This leap directly addresses what the consortium describes as the “insatiable demand for higher bandwidth,” particularly in AI, HPC, and analytics, where interconnect density is a bottleneck.
“You need to deliver more bandwidth in the same physical footprint, but die size won’t grow just because bandwidth requirements do.”
— Debendra Das Sharma, Intel Senior Fellow and UCIe Consortium Chair
Support for Multiple Packaging Types #
The doubled data rates apply to:
- UCIe-S (2D standard packaging)
- UCIe-A (2.5D advanced packaging)
3D packaging remains unchanged, as its micro-bump technology already achieves extreme bandwidth densities—hundreds of terabytes per mm²—well beyond current demand. According to Das Sharma, 2D and 2.5D packaging are where bandwidth gains are most critical.
Seamless Backward Compatibility #
Backward compatibility remains a cornerstone of UCIe 3.0. The consortium’s white paper stresses:
“This ensures that existing systems can migrate to the new specification without disruption, maintaining interoperability with previous-generation devices.”
Broad Industry Applications #
Das Sharma compared UCIe’s role to PCIe at the motherboard level, spanning use cases from handheld devices to hyperscale data centers.
- UCIe-A targets high-bandwidth chiplets, such as AI accelerators.
- UCIe-S serves lower-bandwidth devices.
The vision is a unified standard extending across the computing spectrum:
- Digital Signal Processors (DSPs)
- Wireless infrastructure
- Radar systems
- AI, HPC, and large-scale data centers
“UCIe is everywhere,” Das Sharma said.
“Our goal is to unite the entire industry under one interconnect standard, supporting all major domains of computing.”